A scan controller can test the devices on a scan chain with a minimal amount of extra circuitry. Each device on a scan chain may include a test access port (TAP), and the scan controller may control the TAP of each device using control signals that include a test clock signal, a test mode select signal, a test data input, and a test data output. The scan controller may directly control the test clock signal and the test mode select signal of each device on the scan chain. A sequence of devices may form the scan chain with the test data output of the scan controller connected to the test data input of the first device in the sequence, the test data output of each device in the sequence connected to the test data input to the next device in the sequence until the last device in the sequence, and the test data output of the last device in the sequence connected to the test data input of the scan controller.
The TAP in each device on the scan chain includes a state machine that makes a state transition for each rising edge of the test clock signal to one of two states as selected by the value of the test mode select signal from the scan controller. Even though the TAP in each device on the scan chain may have a separate state machine, generally each state machine is in the same state as controlled by the scan controller.
While the state machines of the TAPs may have synchronized states, the TAP of each device may perform differing tests depended upon the value of an instruction register of the TAP. A shift-instruction state of the state machines of the TAPs of the devices on the scan chain may serially shift one instruction bit from the test data output of the scan controller through the concatenation of the instruction registers of the TAPs of all of the devices on the scan chain. The scan controller may set the instruction registers of each TAP to an individually selected instruction by repeating the shift-instruction state to shift the bits of these instructions through the scan chain.
To set the instruction register of the TAP of each device on the scan chain successfully, the scan controller should have the length of each device's instruction register. If the length of one instruction register is not available, the scan controller might not be able to set the instruction registers of any TAP successfully. Frequently, the configuration, including the length of the instruction register, of the TAP of each device on the scan chain is provided to the scan controller. However, the configuration of certain devices on the scan chain might not be available. For example, the hardware that implements a scan chain may have jumpers that permit the addition of unknown devices to a scan chain. The addition of an unknown device to a scan chain may render the scan chain inoperable for all of the devices on the scan chain.
The present invention may address one or more of the above issues.